Catalog / Verilog Cheatsheet
Verilog Cheatsheet
A comprehensive cheat sheet for Verilog, covering syntax, data types, operators, and common constructs. Useful for digital design and hardware verification.
Syntax and Basic Elements
Modules
Modules are the fundamental building blocks in Verilog.
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Instantiation:
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Data Types
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Represents a physical wire, cannot store values. |
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Represents a variable that stores a value. Used in |
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General-purpose variable, typically 32 bits. |
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Floating-point number. |
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Unsigned 64-bit integer for simulation time. |
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Four-state data type: 0, 1, X (unknown), Z (high impedance). SystemVerilog only. |
Number Representation
Examples:
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Operators
Arithmetic Operators
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Addition |
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Subtraction |
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Multiplication |
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Division |
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Modulo |
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Exponentiation (SystemVerilog) |
Logical Operators
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Logical AND |
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Logical OR |
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Logical NOT |
Bitwise Operators
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Bitwise AND |
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Bitwise OR |
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Bitwise XOR |
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Bitwise NOT |
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Bitwise NAND |
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Bitwise NOR |
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Bitwise XNOR |
Reduction Operators
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Reduction AND |
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Reduction OR |
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Reduction XOR |
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Reduction NAND |
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Reduction NOR |
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Reduction XNOR |
Control Statements
Always Blocks
Describes sequential logic.
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Conditional Statements
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Basic conditional statement.
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Alternative code block.
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Multiple conditions.
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Multi-way branching.
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Loop Statements
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For loop.
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While loop (less common in synthesizable code).
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Advanced Topics
Functions and Tasks
Function: Returns a single value. Cannot contain timing controls or event triggers.
Task: Can have multiple outputs and can contain timing controls.
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Generate Statements
Used for conditional or repetitive instantiation of modules or code blocks at compile time.
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SystemVerilog Constructs (Highlights)
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Four-state data type (0, 1, X, Z), preferred over |
Interfaces |
Bundles signals for easier module connections and verification. |
Assertions |
Used to check design properties dynamically during simulation. |
Clocking Blocks |
Synchronize signals to a specific clock edge for improved timing control. |